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multirate 155 mbps/622 mbps/1244 mbps/1250 mbps burst mode clock and data r ecovery ic with deserializer ADN2855 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2009 analog devices, inc. all rights reserved. features serial data input 155.52 mbps/622.08 mbps/1244.16 mbps/1250.00 mbps 12-bit acquisition time 4-bit parallel lvds output interface patented dual-loop clock recovery architecture integrated prbs generator byte rate reference clock loss-of-lock indicator supports double data rate (ddr)-compatible fpga i 2 c interface to access optional features single-supply operation: 3.3 v power 670 mw typical in serial output mode 825 mw typical in deserializer mode 5 mm 5 mm, 32-lead lfcsp applications passive optical networks gpon/bpon/gepon olt receivers general description the ADN2855 is a burst mode clock and data recovery ic designed for gpon/bpon/gepon optical line terminal (olt) receiver applications. the part can operate at 155.52 mbps, 622.08 mbps, 1244.16 mbps, or 1250.00 mbps data rates, selectable via the i 2 c interface. the ADN2855 frequency locks to the olt reference clock and aligns to the input data within 12 bits of the start of the preamble. the device provides a full rate or an optional half rate output clock for a double data rate (ddr) interface to an fpga or digital asic. all specifications are quoted for ?40c to +85c ambient tempera- ture, unless otherwise noted. the ADN2855 is available in a compact 5 mm 5 mm, 32-lead chip scale package. functional block diagram 2 reset datav datxp, datxn 2 vcc vee sda sck cf1 cf2 pin nin cml input buffer vco phase shifter phase detect frequency/ lock detect data re-timing divider i 2 c deserializer loop filter loop filter 4 2 refclkp, refclkn 06660-001 clkoutp, clkoutn squelch ADN2855 figure 1.
ADN2855 rev. 0 | page 2 of 20 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? jitter specifications ....................................................................... 3 ? output and timing specifications ............................................. 4 ? timing characteristcs .................................................................. 5 ? reset timing options .................................................................. 6 ? absolute maximum ratings ............................................................ 7 ? thermal resistance ...................................................................... 7 ? esd caution .................................................................................. 7 ? pin configuration and function descriptions ............................. 8 ? i 2 c interface timing and internal register description ..............9 ? theory of operation ...................................................................... 11 ? functional description .................................................................. 12 ? frequency acquisition ............................................................... 12 ? squelch mode ............................................................................. 12 ? i 2 c interface ................................................................................ 12 ? reference clock .......................................................................... 13 ? output modes ............................................................................. 14 ? disable output buffers .............................................................. 14 ? applications information .............................................................. 15 ? pcb design guidelines ............................................................. 15 ? outline dimensions ....................................................................... 17 ? ordering guide .......................................................................... 17 ? revision history 1/09revision 0: initial version
ADN2855 rev. 0 | page 3 of 20 specifications t a = t min to t max , vcc = v min to v max , vee = 0 v, c f = 0.47 f, input data pattern: prbs 2 23 ? 1, unless otherwise noted. table 1. parameter conditions min typ max unit input bufferdc characteristics input voltage range @ pin or nin, dc-coupled vcc ? 0.6 vcc ? 0.1 v peak-to-peak differential input pin ? nin 0.2 1.2 v acquisition time (bdr mode 1 ) lock to preamble data 1250.00 mbps 12 bits 1244.16 mbps 12 bits 622.08 mbps 12 bits 155.52 mbps 6 bits power supply voltage 3.0 3.3 3.6 v power supply current serial output mode 204 ma deserializer mode 250 ma operating temperature range ?40 +85 c 1 bdr mode = burst clock and data recovery mode, whereas cdr = continuous clock and data recovery mode. jitter specifications t a = t min to t max , vcc = v min to v max , vee = 0 v, c f = 0.47 f, input data pattern: prbs 2 23 ? 1, unless otherwise noted. table 2. parameter conditions min typ max unit phase-locked loop characteristics jitter tolerance 1250.00 mbps, 2 23 ? 1 prbs 50 khz 3.0 ui p-p 500 khz 1.0 ui p-p 10 mhz 0.5 ui p-p 1244.16 mbps, 2 23 ? 1 prbs 50 khz 3.0 ui p-p 500 khz 1.0 ui p-p 10 mhz 0.5 ui p-p 622.08 mbps, 2 23 ? 1 prbs 25 khz 2.5 ui p-p 250 khz 1.0 ui p-p 155.52 mbps, 2 23 ? 1 prbs 6.5 khz 3.5 ui p-p 65 khz 1.0 ui p-p
ADN2855 rev. 0 | page 4 of 20 output and timing specifications table 3. parameter symbol conditions min typ max unit lvds ouput characteristics clkoutp/clkoutn, datxp/datxn differential output swing v diff see figure 3 260 320 400 mv output high voltage v oh 1475 mv output low voltage v ol 925 mv output offset voltage v os 1125 1200 1275 mv output impedance differential 100 lvds outputs timing rise time 20% to 80% 115 220 ps fall time 80% to 20% 115 220 ps setup time t s 0.5 ? 20% 0.5 ui hold time t h 0.5 ? 20% 0.5 ui i 2 c interface dc characteristics (sck, sda) lvcmos input high voltage v ih 0.7 vcc v input low voltage v il 0.3 vcc v input current v in = 0.1 vcc or v in = 0.9 vcc ?10.0 +10.0 a output low voltage v ol i ol = 3.0 ma 0.4 v i 2 c interface timing sck clock frequency 400 khz sck pulse width high t high 600 ns sck pulse width low t low 1300 ns start condition hold time t hd;sta 600 ns start condition setup time t su;sta 600 ns data setup time t su;dat 100 ns data hold time t hd;dat 300 ns sck and sda rise/fall time t r /t f 20 + 0.1 cb 1 300 ns stop condition setup time t su;sto 600 ns bus free time between a stop and a start t buf 1300 ns refclk characteristics at refclkp or refclkn input voltage range v il 0 v v ih vcc v minimum differential input drive 100 mv p-p reference frequency 10 155.52 200 mhz required accuracy 0 ppm lvttl dc input characteristics (squelch, saddr[2:1], reset) input high voltage v ih 2.0 v input low voltage v il 0.8 v input high current i ih v in = 2.4 v 5 a input low current i il v in = 0.4 v ?5 a lvttl dc output characteristics ( datav ) output high voltage v oh i oh = ?2.0 ma 2.4 v output low voltage v ol i ol = 2.0 ma 0.4 v 1 c b = total board capacitance of one bus line in picofarads (pf). if mixed with high speed class of i 2 c devices, faster fall times are allowed.
ADN2855 rev. 0 | page 5 of 20 timing characteristcs c lkoutp datxp/ datxn t s t h 06660-102 figure 2. output timing outp outn outp ? outn 0v v se v lvds v se v diff 06660-103 figure 3. single-ended vs. differential output specifications 06660-003 clkoutp dat0p/ dat0n t h t s figure 4. serial output mode (full rate clock) 06660-004 dat0p/ dat0n clkoutp t h t s figure 5. serial output mode (half rate clock, ddr mode) 06660-005 datxp/ datxn clkoutp t h t s figure 6. nibble output mode (full rate clock) 06660-006 datxp/ datxn clkoutp t h t s figure 7. nibble output mode (half rate clock, ddr mode)
ADN2855 rev. 0 | page 6 of 20 reset timing options 06660-007 option 1 end of packet option 2 end of packet option 3 end of packet reset pulse 0 bytes to 8 bytes 0 bytes to 8 bytes reset pulse (2 bytes) 200s between bursts 200s between bursts reset pulse (2 bytes) guard time (4 bytes) this assumes no noise is present on the inputs to the ADN2855 this assumes no noise is present at the inputs to the ADN2855 between bursts. if this is the case, the reset pulse must beasserted until the time that the input data to the ADN2855 becomes valid, ideally just prior to the start of the preamble. there is no requirement that following the deassertion of the reset signal the ADN2855 must see at least 13 bits of the preamble. figure 8. reset timing options
ADN2855 rev. 0 | page 7 of 20 absolute maximum ratings t a = t min to t max , vcc = v min to v max , vee = 0 v, c f = 0.47 f, unless otherwise noted. table 4. parameter rating supply voltage (vcc) 4.2 v minimum input voltage (all inputs) vee ? 0.4 v maximum input voltage (all inputs) vcc + 0.4 v maximum junction temperature 125c storage temperature range ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for 4-layer board with exposed paddle soldered to vee. table 5. thermal resistance package type ja jc unit 32-lead lfcsp (cp-32-3) 35.1 2.4 c/w esd caution
ADN2855 rev. 0 | page 8 of 20 pin configuration and fu nction descriptions 06660-002 sck refclkp refclkn vcc vee cf2 cf1 vcc vee squelch clkoutn clkoutp vcc dat0p dat0n saddr[2] reset saddr[1] nin pin vcc vee sda vcc vee dat1p dat1n notes 1. there is an exposed pad on the bottom of the package that must be connected to vee (gnd). dat2p dat2n dat3p dat3n pin 1 indicator 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 top view (not to scale) ADN2855 datav figure 9. pin configuration table 6. pin function descriptions pin no. mnemonic type 1 description 1 saddr[2] di slave address bit 2. 2 reset di reset pulse to be asserted prior to incoming burst. active high. 3 saddr[1] di slave address bit 1. 4 nin ai differential data input. cml. 5 pin ai differential data input. cml. 6 vcc p 3.3 v power. 7 vee p gnd. 8 sda io i 2 c data i/o. 9 sck di i 2 c clock. 10 refclkp di differential refclk input. 11 refclkn di differential refclk input. 12 vcc p 3.3 v power. 13 vee p gnd. 14 cf2 ao frequency loop capacitor. 15 cf1 ao frequency loop capacitor. 16 datav do output data valid. lvttl active low. 17 dat3n do differential deserialized output msb, lvds. 18 dat3p do differential deserialized output msb, lvds. 19 dat2n do differential deserialized output bit 2, lvds. 20 dat2p do differential deserialized output bit 2, lvds. 21 dat1n do differential deserialized output bit 1, lvds. 22 dat1p do differential deserialized output bit 1, lvds. 23 vee p gnd. 24 vcc p 3.3 v power. 25 dat0n do differential deserialized output lsb, lvds 26 dat0p do differential deserialized output lsb, lvds 27 vcc p 3.3 v power 28 clkoutp do differential recovered clock output, lvds. 29 clkoutn do differential recovered clock output, lvds. 30 squelch di squelch data and/ or clock outputs. active high. 31 vee p gnd 32 vcc p 3.3 v power. 33 (epad) exposed pad (epad) p there is an exposed pad on the bottom of the package that must be connected to vee (gnd). 1 p = power, ai = analog input, ao = analog output, di = digital input, do = digital output, io = digital input/output.
ADN2855 rev. 0 | page 9 of 20 i 2 c interface timing and intern al register description 06660-008 saddr[7:1] 113x 0000 pin pin r/w ctrl 0 = w 1 = r figure 10. slave address configuration 0 6660-00 9 s slave addr, lsb = 0 (wr) a(s) a(s) a(s) data sub addr a(s) p data figure 11. i 2 c write data transfer 06660-010 s s = start bit p = stop bit a(s) = acknowledge by slave a(m) = acknowledge by master a(m) = lack of acknowledge by master s slave addr, lsb = 0 (wr) slave addr, lsb = 1 (rd) a(s) a(s) sub addr a(s) data a(m) data p a(m) figure 12. i 2 c read data transfer 06660-011 start bit s stop bit p ack ack wr ack d0 d7 a0 a7 a5 a6 saddr[4:0] slave address sub address data sub addr[6:1] data[6:1] sck sda figure 13. i 2 c data transfer timing 06660-012 t buf sda ssps sck t f t low t r t f t hd;sta t hd;dat t su;dat t high t su;sta t su;sto t hd;sta t r figure 14. i 2 c port timing diagram
ADN2855 rev. 0 | page 10 of 20 table 7. internal register map 1 reg. name r/w address d7 d6 d5 d4 d3 d2 d1 d0 ctrla w 0x08 f ref range data rate/div_f ref ratio 0 lock to refclk ctrla_rd r 0x05 readback ctrla ctrlb w 0x09 0 0 initiate acquisition 0 0 0 0 0 ctrlb_rd r 0x06 readback ctrlb ctrlc w 0x11 0 0 bus swap parallel clkout mode rxclk phase adjust 0 output boost ctrld w 0x22 output mode disable data buffer disable clock buffer 0 0 0 0 serial clkout mode 1 all writeable registers default to 0x00. table 8. control register, ctrla 1 bit no. description [7:6] f ref range 00 = 10 mhz to 25 mhz 01 = 25 mhz to 50 mhz 10 = 50 mhz to 100 mhz 11 = 100 mhz to 200 mhz [5:2] data rate/div_f ref ratio 0000 = 1 0001 = 2 0010 = 4 n = 2 n 1000 = 256 [1] set to 0 [0] lock to rfclk 0 = lock to input data 1 = lock to reference clock 1 where div_f ref is the divided down reference referred to the 10 mhz to 20 mhz band (see the reference clock section). table 9. control register, ctrlb bit no. description [7:6] set to 0 [5] initiate acquisition; write a 1 followed by 0 to initiate a new acquisition [4:0] set to 0 table 10. control register, ctrlc bit no. description [7:6] set to 0 [5] bus swap 0 = dat3 is earliest bit 1 = dat0 is earliest bit [4] parallel clkout mode 0 = full rate parallel clock 1 = half rate parallel clock (ddr mode) [3:2] rxclk phase adjust 00 = clk edge in center of eye 01 = +2 ui vs. baseline (clk edge aligned with data transition) 10 = +0.5 ui vs. baseline 11 = ?1.5 ui vs. baseline [1] set to 0 [0] output boost 0 = default 1 = boost output swing table 11. control register, ctrld bit no. description [7] output mode 0 = parallel output 1 = serial output [6] disable data buffer 0 = default 1 = disable data output buffer [5] disable clock buffer 0 = default 1 = disable clock output buffer [4:1] set to 0 [0] serial clkout mode 0 = half rate serial clock 1 = full rate serial clock
ADN2855 rev. 0 | page 11 of 20 theory of operation the ADN2855 is designed specifically for burst mode data recovery in gpon/bpon/gepon optical line terminal (olt) receivers. the ADN2855 requires a reference clock that is frequency locked to the incoming data. the fll (frequency-locked loop) of the ADN2855 acquires frequency lock with respect to this reference clock, pulling the vco towards 0 ppm frequency error. it is assumed that the upstream bursts to the olt are clocked by the recovered clock from the optical network terminal (ont) cdr. this guarantees frequency lock to the olt system clock. the ADN2855 has a preamble detector that looks for a maximum transition density pattern (1010) within the preamble. once this pattern is detected in the preamble, the on-chip delay/phase- locked loop (d/pll) quickly acquires phase lock to the incoming burst within 12 ui of the 1010 pattern. the d/pll also pulls in any remaining frequency error that was not pulled in by the fll. the incoming data is retimed by the recovered clock and output either serially or in a 4-bit parallel output nibble. the ADN2855 requires a reset signal between bursts to set the device into a fast phase acquisition mode. the reset signal must be asserted within 8 ui of the end of the previous burst, and it must be deasserted prior to the start of the maximum transition density portion of the preamble, which is specifically provided for the burst mode clock recovery device to acquire the phase of the incoming burst. the reset signal must be at least 16 ui wide. see the reset timing options section for more details.
ADN2855 rev. 0 | page 12 of 20 functional description frequency acquisition the ADN2855 operates in burst data recovery mode, which requires the use of the olt system reference clock as an acqui- sition aid. the ADN2855 acquires frequency with respect to this reference clock, which is frequency locked to the incoming burst of data from the ont. the ADN2855 must be placed in lock to reference clock mode by setting ctrla[0] = 1. a frequency acquisition is then initiated by writing a 1 to 0 transition into ctrlb[5]. this must be done well before the ADN2855 is expected to lock to an incoming burst, preferably right after power-up and once there is a valid reference clock being supplied to the device. as long as the reference clock to the ADN2855 is always present, this frequency acquisition needs to take place only once. it does not need to be repeated between bursts of data in its normal operating mode. the initial frequency acquisition with respect to the reference clock takes ~10 ms. to lock to burst data, a reset signal must be asserted following a previous burst (or at startup) according to the timing diagrams shown in the reset timing options section. the reset signal must be deasserted prior to the 1010 portion of the preamble. the ADN2855 uses a preamble detector that identifies the 1010 portion of the preamble and quickly acquires the phase of the incoming burst within 12 ui. the frequency loop requires a single external capacitor between pin 14, cf2, and pin 15, cf1. a 0.47 f 20%, x7r ceramic chip capacitor with <10 na leakage current is recommended. leakage current of the capacitor can be calculated by dividing the maximum voltage across the 0.47 f capacitor, ~3 v, by the insulation resistance of the capacitor. the insulation resistance of the 0.47 f capacitor should be greater than 300 m. datav operation the ADN2855 has a data valid indicator that asserts when the ADN2855 acquires the phase of the maximum transition density portion of the preamble. this takes 12 ui from the start of the 1010 pattern in the preamble. the datav output remains asserted until the reset signal is asserted following the end of the current burst of data, at which point the datav output deasserts. the datav output is active low and is lvttl compatible. squelch mode when the squelch input, pin 30, is driven to a ttl high state, both the clock and data outputs are set to the zero state to suppress downstream processing. if the squelch function is not required, pin 30 should be tied to vee. if it is desired that the datxp/datxn and clkoutp/ clkoun outputs be squelched while the output data is invalid, then the datav pin can be hardwired directly to the squelch input. i 2 c interface the ADN2855 supports a 2-wire, i 2 c-compatible serial bus driving multiple peripherals. two inputs, serial data (sda) and serial clock (sck), carry information between any devices con- nected to the bus. each slave device is recognized by a unique address. the ADN2855 has four possible 7-bit slave addresses for both read and write operations. the msb of the 7-bit slave address, saddr[7] is factory programmed to 1. bit 2 of the slave address, saddr[2], is set by pin 1. bit 1 of the slave address, saddr[1], is set by pin 3. slave address bits[6:3] are defaulted to all 0s. the slave address consists of the seven msbs of an 8-bit word. the lsb of the word, saddr[0], sets either a read or write operation (see figure 10). logic 1 corresponds to a read operation, and logic 0 corresponds to a write operation. to control the device on the bus, use the following protocol. first, the master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on sda while sck remains high. this indicates that an address/data stream follows. all peripherals respond to the start condition and shift the next eight bits (the 7-bit address and the r/w bit). the bits are transferred from msb to lsb. the peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. this is known as an acknowledge bit. all other devices withdraw from the bus at this point and maintain an idle condition. the idle condition is where the device monitors the sda and sck lines waiting for the start condition and correct transmitted address. the r/w bit determines the direction of the data. logic 0 on the lsb of the first byte means that the master writes information to the peripheral. logic 1 on the lsb of the first byte means that the master reads information from the peripheral. the ADN2855 acts as a standard slave device on the bus. the data on the sda pin is eight bits long supporting the 7-bit addresses plus the r/w bit. the ADN2855 has six subaddresses to enable the user-accessible internal registers (see table 7 through table 11). it, therefore, interprets the first byte as the device address and the second byte as the starting subaddress. autoincrement mode is supported, allowing data to be read from or written to the starting subaddress and each subsequent address without manually addressing the subsequent subaddress. a data transfer is always terminated by a stop condition. the user can also access any unique subaddress register on a one-by-one basis without updating all registers. stop and start conditions can be detected at any stage of the data transfer. if these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition. during a given sck high period, the user should issue one start condition, one stop condition, or a single stop condition followed by a single start condition. if an invalid subaddress is issued by the user, the ADN2855 does not issue an acknowledge, and returns to the idle condition. if the
ADN2855 rev. 0 | page 13 of 20 user exceeds the highest subaddress while reading back in autoincrement mode, then the highest subaddress register contents continue to be output until the master device issues a no-acknowledge. this indicates the end of a read. in a no- acknowledge condition, the sdata line is not pulled low on the ninth pulse. see figure 11 and figure 12 for sample write and read data transfers and figure 13 for a more detailed timing diagram. reference clock a reference clock is required to perform burst mode clock and data recovery with the ADN2855. the reference clock must be frequency locked to the incoming burst data. it is assumed that the incoming burst data from the ont is timed by a clock recov- ered from the downstream data from the olt and, therefore, is inherently frequency clocked to the olt system clock. the reference clock can be driven differentially or single-ended. see figure 15 and figure 16 for sample configurations. the refclk input buffer accepts any differential signal with a peak-to-peak differential amplitude of greater than 100 mv (for example, lvpecl or lvds) or a standard single-ended low voltage ttl input, providing maximum system flexibility. phase noise and duty cycle of the reference clock are not critical. 06660-013 refclkp refclkn 100k ? 100k ? buffer vcc/2 11 10 figure 15. differential refclk configuration 06660-014 refclkp refclkn 100k ? 100k ? buffer vcc/2 out v c c osc clk 11 10 figure 16. single-ended refclk configuration the ADN2855 must be operated in lock to reference clock mode when in burst data recovery mode. lock to reference clock mode is enabled by writing a 1 to i 2 c control register ctrla, bit 0. a frequency acquisition in this mode must be initiated by writing a 1 to 0 transition to ctrlb[5]. using the reference clock to lock onto data in this mode, the ADN2855 locks onto a frequency derived from the reference clock according to the following equation: data rate /2 ctrla[5:2] = refclk /2 ctrla[7:6] the user must know exactly what the data rate is and provide a reference clock that is a function of this rate. the reference clock can be anywhere between 10 mhz and 200 mhz. by default, the ADN2855 expects a reference clock of between 10 mhz and 25 mhz. if it is between 25 mhz and 50 mhz, 50 mhz and 100 mhz, or 100 mhz and 200 mhz, the user needs to configure the ADN2855 to use the correct reference frequency range by setting two bits of the ctrla register, ctrla[7:6]. table 12. ctrla settings bit no. description ctrla[7:6] f ref range 00 = 10 mhz to 25 mhz 01 = 25 mhz to 50 mhz 10 = 50 mhz to 100 mhz 11 = 100 mhz to 200 mhz ctrla[5:2] data rate/div_f ref ratio 0000 = 1 0001 = 2 n = 2 n 1000 = 256 the user can specify a fixed integer multiple of the reference clock to lock onto using ctrla[5:2], where ctrla should be set to the data rate/div_f ref ratio, where div_f ref represents the divided-down reference referred to the 10 mhz to 25 mhz band. for example, if the reference clock frequency is 38.88 mhz and the input data rate is 622.08 mbps, then ctrla[7:6] should be set to 01 to give a divided-down reference clock of 19.44 mhz. ctrla[5:2] should be set to 0101, that is, 5, because 622.08 mbps/19.44 mhz = 2 5 while the ADN2855 is operating in lock to reference clock mode, if the user ever changes the reference frequency, the f ref range (ctrla[7:6]), or the data rate/div_f ref ratio (ctrla[5:2]), this must be followed by writing a 0 to 1 transition into the ctrlb[5] bit to initiate a new frequency acquisition.
ADN2855 rev. 0 | page 14 of 20 output modes parallel or serial output mode the output of the ADN2855 can be configured in a 4-bit parallel output nibble mode, or it can be configured in a serial output mode. the default mode of operation is for the rx data to be deserialized and output in a 4-bit nibble, present at datxp/datxn, where the earliest bit is present on dat3p/dat3n. setting bit ctrlc[5] = 1 reverses the order of the datxp/datxn bus such that the earliest bit is present on dat0p/dat0n. setting bit ctrld[7] = 1 puts the device into serial output mode. in this mode, the rx data is present on dat0p/dat0n. double data rate mode the default output mode for the ADN2855 is for a 4-bit deseria- lized output with a full rate output clock, where the output data switches on the rising edge of the output clock. when the ADN2855 is programmed to be in parallel output mode (ctrld[7] = 0), setting ctrlc[4] = 1 puts the ADN2855 clock output through divide-by-two circuitry, allowing direct interfacing to fpgas that support data clocking on both rising and falling edges. when the ADN2855 is in serial output mode (deserializer off), ctrld[7] = 1, the default is for a half rate output clock where the data switches on both falling and rising edges of the output clock. setting ctrld[0] = 1 sets the serial clock output into full rate mode so that the output data switches only on the rising edges of the output clock. rxclk phase adjust the ADN2855 provides the option of adjusting the phase of the output clock with respect to the parallel output data. in parallel mode, the duration of each bit is 4 ui wide, due to the deserializa- tion. there are three additional phase adjust options other than the baseline (that is, clk edge in the center of the data eye): +2 ui, +0.5 ui, and ?1.5 ui. the output clock phase adjustment feature is accessed via ctrlc[3:2]. see table 10 for details. disable output buffers the ADN2855 provides the option of disabling the output buffers for power savings. the clock output buffers can be disabled by setting ctrld[5] = 1. for additional power savings (for example, in a low power standby mode), the data output buffers can also be disabled by setting ctrld[6] = 1.
ADN2855 rev. 0 | page 15 of 20 applications information pcb design guidelines proper rf pcb design techniques must be used for optimal performance. power supply connections and ground planes use of one low impedance ground plane is recommended. the vee pins should be soldered directly to the ground plane to reduce series inductance. if the ground plane is an internal plane and connections to the ground plane are made through vias, multiple vias can be used in parallel to reduce the series inductance. the exposed pad should be connected to the gnd plane using plugged vias so that solder does not leak through the vias during reflow. use of a 10 f electrolytic capacitor between vcc and vee is recommended at the location where the 3.3 v supply enters the pcb. when using 0.1 f and 1 nf ceramic chip capacitors, they should be placed between the ic power supply vcc and vee, as close as possible to the ADN2855 vcc pins. if connections to the supply and ground are made through vias, the use of multiple vias in parallel helps to reduce series inductance. refer to the schematic in figure 17 for recommended connections. by using adjacent power supply and gnd planes, excellent high frequency decoupling can be realized by using close spacing between the planes. this capacitance is given by ? ? a/d c r plane 88.0pf ? where: r is the dielectric constant of the pcb material. a is the area of the overlap of power and gnd planes (cm 2 ). d is the separation between planes (mm). for fr-4, r = 4.4 mm and 0.25 mm spacing, c plane 15 pf/cm 2 . 06660-015 vco freq, lock det phase det phase shifter loop filter loop filter i 2 c deserializer divider data retiming refclkp, refclkn datxp, datxn clkoutp, clkoutpn cf1 cf2 vcc 0.1f 0.47f v cc vee pin nin pin v pd nin laoutp laoutn sda sck saddr[2:1] datav reset vee vcc reset squelch squelch cml input buffer 2 4 2 2 2 0.1f 1nf vcc olt system clock ADN2855 olt mac vcc 0.1f figure 17. typical application circuit
ADN2855 rev. 0 | page 16 of 20 transmission lines use of 50 transmission lines is required for all high frequency input and output signals to minimize reflections: pin, nin, clkoutp, clkoutn, datxp, datxn (also refclkp and refclkn if a high frequency reference clock is used, such as 155.52 mhz). it is also necessary for the pin/nin input traces to be matched in length, and the clkoutp/clkoutn and datxp/datxn output traces to be matched in length to avoid skew between the differential traces. all high speed lvds outputs, clkoutp/clkoutn and datxp/datxn, require a 100 differential termination at the differential input to the device being driven by the ADN2855 outputs. the high speed inputs, pin and nin, are internally terminated with 50 to an internal reference voltage. as with any high speed mixed-signal design, take care to keep all high speed digital traces away from sensitive analog nodes. soldering guidelines for chip scale package the lands on the 32-lead lfcsp are rectangular. the pcb pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. the land should be centered on the pad to ensure that the solder joint size is maximized. visit www.analog.com/cp-32-3 for further details. the bottom of the chip scale package has a central exposed pad. the pad on the pcb should be at least as large as this exposed pad. the user must connect the exposed pad to vee (gnd) using plugged vias so that solder does not leak through the vias during reflow. this ensures a solid connection from the exposed pad to vee.
ADN2855 rev. 0 | page 17 of 20 outline dimensions compliant to jedec standards mo-220-vhhd-2 0.30 0.23 0.18 0.20 ref 0.80 max 0.65 typ 0.05 max 0.02 nom 12 max 1.00 0.85 0.80 seating plane coplanarity 0.08 1 32 8 9 25 24 16 17 0.50 0.40 0.30 3.50 ref 0.50 bsc pin 1 indicator top view 5.00 bsc sq 4.75 bsc sq 3.45 3.30 sq 3.15 pin 1 indicator 0.60 max 0.60 max 0.25 min exposed pad (bottom view) 112408-a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 18. 32-lead lead frame chip scale package [lfcsp_vq] 5 mm 5 mm body, very thin quad (cp-32-3) dimensions shown in millimeters ordering guide model temperature range packag e description package option ADN2855acpz 1 ?40c to +85c 32-lead lead frame chip scale package [lfcsp_vq] cp-32-3 ADN2855acpz-r7 1 ?40c to +85c 32-lead lead frame chip scale package [lfcsp_vq] cp-32-3 ADN2855-evalz 1 evaluation board 1 z = rohs compliant part.
ADN2855 rev. 0 | page 18 of 20 notes
ADN2855 rev. 0 | page 19 of 20 notes
ADN2855 rev. 0 | page 20 of 20 notes ?2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d06660-0-1/09(0)

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